JNCASR Scientists Passed Terahertz Waves Through an Engineered Barrier on a Silicon Chip With 1 to 3 Per Cent Loss and Carried Data at Up to 100 Gbit/s, a Step Toward 6G Circuits

Researchers at the Jawaharlal Nehru Centre for Advanced Scientific Research (JNCASR) in Bengaluru have built a silicon chip on which terahertz waves cross a deliberately placed barrier with about 1 to 2 per cent loss. A second barrier in sequence brings the loss to about 2 to 3 per cent. On one of the three test devices, a power splitter with a barrier in one branch, the chip carried data at 100 gigabits per second. JNCASR is an autonomous institute of the Department of Science and Technology (DST), which announced the result through the Press Information Bureau on 4 November 2026. The work is published in the journal Advanced Materials.

What the chip does

Terahertz waves sit between microwaves and infrared light on the spectrum. The PIB release says future sixth-generation (6G) wireless networks are expected to use these frequencies because they offer wide bandwidth. Getting such waves around a compact circuit is the hard part: bends, junctions and abrupt changes in a waveguide (the channel that guides a wave) scatter or reflect part of the signal.

JNCASR’s own research page for the group describes the same problem, listing reflection and scattering losses at sharp bends or defects as the obstacle for on-chip terahertz devices. The group’s answer is topological photonics, a branch of optics in which a wave travelling along the boundary between two differently built regions resists certain kinds of backscattering.

Triangular holes and a barrier made of geometry

The team etched triangular holes into a silicon slab in a pattern that mimics the honeycomb lattice of graphene. Two regions with slightly different hole sizes meet along a boundary, and terahertz waves travel along that boundary. The researchers then built the barrier by changing the sizes of the holes over a short stretch of the waveguide.

In a conventional waveguide that is not topological, the PIB release says, a comparable barrier markedly reduces transmission. On the JNCASR chip, transmission stayed close to its barrier-free level as long as the barrier strength stayed below a characteristic coupling strength of the crystal. Because the barrier is set purely by hole geometry, the release calls this a practical design rule.

The release names the underlying effect in a figure caption as photonic Klein tunnelling. Physicists know the Klein paradox as the perfect passage of relativistic particles through high barriers, and a 2022 paper in Physical Review Letters describes it as responsible for the exceptional conductive properties of graphene. A 2017 preprint had already described one-way Klein tunnelling for light in photonic topological insulators, and the Physical Review Letters paper reported perfect Klein transmission in a two-dimensional photonic system, using a vapour of atoms rather than a chip.

Three devices, three data rates

All three devices were fabricated on high-resistivity silicon, which the release describes as compatible with established semiconductor manufacturing. Measurements across 310 to 360 GHz agreed closely with simulations. According to the release:

• Two barriers in sequence: 48 Gbit/s in the high-speed data test.
• An omega-shaped route with four sharp bends and a central barrier: 60 Gbit/s.
• A power splitter with a barrier in one of its two branches: 100 Gbit/s using QAM-32 modulation, a scheme that encodes information in the signal’s amplitude and phase.

In the splitter, the two output signals were nearly identical, which the release reads as showing that the barrier had little effect on transmission. The release adds that at 100 Gbit/s a 5-gigabyte high-definition film could in principle be transferred in under half a second.

The lab behind it

The study was led by Dr Abhishek Kumar, Assistant Professor at JNCASR, who heads the Meta Optics Laboratory there. Samina Mulla and Sangram Kumar Sadhu of JNCASR are the joint first authors. Collaborators named in the release come from IISER Kolkata, IIT Bombay, the Institute of Microelectronics at A*STAR in Singapore, and the University of Lille and CNRS in France, along with other JNCASR researchers.

Kumar’s JNCASR profile says he finished his integrated BS-MS at IISER Kolkata in 2016, took a PhD in physics and applied physics at Nanyang Technological University in Singapore in 2020, and did postdoctoral work at the Centre for Disruptive Photonic Technologies in Singapore on silicon topological terahertz photonics for 6G devices. He joined JNCASR in August 2023.

The new chip follows a line of silicon terahertz work. A 2019 preprint by Yihao Yang and seven co-authors, among them Ranjan Singh, reported valley-polarised topological transport on all-silicon chips, with full transmission through ten sharp corners and error-free communication at 10 Gbit/s through a twisted domain wall. In 2022 Kumar was first author of a Nature Communications paper reporting a single-channel 160 Gbit/s link and a silicon demultiplexer, with 40 Gbit/s signals separated and uncompressed high-definition video streamed in real time. The University of Lille’s PhLAM laboratory, a collaborator on that paper, notes that Web of Science lists it as a hot paper, cited in the top 0.1 per cent of physics papers. Kumar was also first author of a 2024 Nature Communications paper on slow light in topological waveguides.

Where 6G stands and what the team plans next

The International Telecommunication Union calls the next generation IMT-2030. Its radiocommunication study group published a report on the technical feasibility of mobile technology in bands above 100 GHz in May 2024, and as of 6 November 2026 its page says proposals for candidate radio technologies will be received from February 2027 to February 2029. The JNCASR measurements at 310 to 360 GHz fall in the range above 100 GHz that the ITU report covers. The ITU also says its minimum requirements do not represent guaranteed real-world deployment performance.

The JNCASR result is a laboratory demonstration of circuit components on chips, not a network. India’s own 6G work, including the Bharat 6G Alliance’s symposium at the India Mobile Congress in October 2026, covers networks and standards. The chip sits at the component end of that effort, and the release’s point that silicon suits established chip manufacturing connects it to the plants described in India’s semiconductor fab race. The release does not say whether the measured losses and data rates have been reproduced elsewhere.

The team’s next step, according to the release, is to tune the barriers electrically, thermally or mechanically, which could let one device redirect signals between paths on demand. Kumar is quoted in the release saying that crossing a barrier made simply by changing the hole geometry, at 100 gigabits per second, suggests the effect can become a useful design tool for terahertz chips.