IIT Madras's SHAKTI Open Processor Has Produced Three Chips at India's SCL Fab, From RIMO in 2018 to the IRIS Space Controller Booted With ISRO in 2025

On 11 February 2025 IIT Madras and ISRO announced that IRIS, a 64-bit controller chip for space systems, had been designed, made, packaged, mounted on a board and booted, all of it inside India according to IIT Madras. The chip is built on SHAKTI, IIT Madras’s family of open processor designs. Prof. V. Kamakoti, the institute’s director and the leader of the SHAKTI project, said it was the third SHAKTI chip fabricated at the Semi-Conductor Laboratory (SCL) in Chandigarh, after RIMO in 2018 and MOUSHIK in 2020.

SHAKTI is a set of processor designs that anyone may read, copy and change, and several chips have been made from them. The sources show what the family is, which chips exist, what SCL can make, what ISRO asked for in IRIS, and which programme and companies have grown around the cores.

A processor design that anyone can read

Every processor follows an instruction set architecture, the list of operations it understands. The SHAKTI motivation page says the dominant sets are licensed: Intel licenses its set to few users, Arm charges licence fees and royalties, and some licences run to 1 to 10 million US dollars. RISC-V, which grew out of a research project at the University of California, Berkeley, is an open standard whose ratified specifications, RISC-V International says, are royalty free. SHAKTI cores implement it. The project’s home page says the source code of the SHAKTI components is open under a three-part BSD licence, which Kamakoti said in a 2019 interview lets anyone modify the design without telling the team. He added that the designs are written in Bluespec SystemVerilog, a hardware description language.

Kamakoti gave his reason for starting in the same interview. A processor bought from abroad is a black box, he said: a buyer can confirm that it does what is wanted but never that it does nothing else, so every country should have its own. The name comes from the first open processor the team looked at, IBM’s POWER. Power in Sanskrit is shakti, he said. The team found OpenPOWER less open than it had hoped and moved to RISC-V, and he describes IIT Madras as one of the early founding members of the RISC-V foundation.

The sources give three start years. Kamakoti dates the programme to 2012. The project’s own slides say SHAKTI was born in 2013, when the team explored instruction sets and was approached by Berkeley to adopt RISC-V. The project’s website says it began as an academic initiative in 2014. Funding from the Ministry of Electronics and Information Technology (MeitY) is dated 2018 in the slides, when the India Microprocessor Development Programme began. Kamakoti said in 2019 that his group had received a MeitY grant of around Rs 11 crore and that an alumnus had sponsored about one million US dollars for a centre he called C-DISHA. IIT Madras’s 2025 release places the project in the Prathap Subrahmanyam Centre for Digital Intelligence and Secure Hardware Architecture.

Three classes of core

The processors page describes a family arranged by size. The E class is a three-stage, in-order embedded core for low-power work such as smart cards, motor controls and robots. The C class is a five-stage in-order controller core with memory management, able to run Linux, aimed at a clock range of 0.5 to 1.5 GHz. The I class adds out-of-order execution and multithreading, with a target of 1.5 to 2.5 GHz. Multicore and server-oriented classes, and two experimental ones for tagged memory and fault tolerance, are described on the same page as plans or research.

The chips, from Oregon to Chandigarh

IIT Madras described the 2018 SCL chips, as reported by IANS, as the first RISC-V microprocessor designed and made completely in India. Kamakoti described the plan in 2019: the design at IIT Madras’s RISE laboratory, fabrication at SCL, and validation on a motherboard built at the institute. He added that the two chips, the Intel one and the SCL one, were made within about six months of each other.

The process sets the ceiling on speed. Kamakoti said in 2019 that 180 nm, the process SCL runs, could give up to 100 MHz, and perhaps 150 to 200 MHz after small additions by the fab. The IANS report of the 2018 announcement noted that many applications need processors below 200 MHz.

What SCL is

The Semi-Conductor Laboratory describes itself as an autonomous body under MeitY and the only integrated device manufacturing facility in the country, covering design, fabrication, packaging, testing and reliability assurance. It was formerly Semiconductor Complex Limited, a government enterprise, and was converted into a laboratory under the Department of Space on 1 September 2006. Its administrative control moved from the Department of Space to MeitY under a notification of 7 February 2022. IANS’s 2018 report describes SCL as ISRO’s, which fits the years it sat under the Department of Space.

SCL says it has an 8-inch wafer line qualified to a JEDEC standard at a 180 nm CMOS node, with 1.8 V, 1.8/3.3 V or 1.8/5 V supply options and four to six aluminium metal layers, plus a 6-inch line for micro-electromechanical devices. IIT Madras’s releases place SCL in Chandigarh and a PIB release places it in Mohali. The commercial chip plants approved under the India Semiconductor Mission, which are a separate programme, are covered in the semiconductor fab race article.

IRIS, a controller conceived at ISRO

IRIS stands for Indigenous RISC-V Controller for Space Applications. IIT Madras’s release says the idea came from the Inertial Systems Unit of ISRO (IISU) in Thiruvananthapuram, which proposed a 64-bit RISC-V controller and worked with IIT Madras on the specification. The configuration was set from the common needs of sensors and systems used in ISRO missions. Fault-tolerant internal memories were attached to the SHAKTI core, and custom modules used in space systems were added: a CORDIC unit (a hardware block for trigonometric calculation), watchdog timers and advanced serial buses. Multiple boot modes and memory extension interfaces leave room for later missions. The project’s tape-out page lists the core as a C class design in 180 nm CMOS in a 17 mm by 17 mm, 219-pin ball grid package.

The release names each stage of the chain. SCL made the chip. Tata Advanced Systems packaged it at Perjenahalli in Karnataka. PCB Power in Gujarat made the motherboard, Syrma SGS in Chennai assembled and mounted it, and IIT Madras wrote the software and booted it. SCL’s director general, Kamaljeet Singh, said the chip was fabricated in SCL’s 180 nm technology including mask frame design, GDS preparation and testing, and that wafer-level validation was done at SCL with the IIT Madras team.

ISRO’s chairman, Dr V. Narayanan, called it a milestone for “Make in India” in semiconductor design and fabrication. He also said:

It is planned to flight test a product based on this controller shortly and performance will be confirmed.

None of the sources opened for this article reports a flight result as of 5 November 2026.

The programme and the companies around it

On 27 April 2022 MeitY announced the Digital India RISC-V (DIR-V) programme, with milestones of commercial silicon and design wins for SHAKTI and for C-DAC’s VEGA processors by December 2023. Kamakoti was named chief architect and S. Krishnakumar Rao programme manager. C-DAC’s earlier work on supercomputers is told in the PARAM article.

A PIB release of 17 November 2023 listed the tape-outs under the programme: 32-bit and 64-bit SHAKTI processors at 180 nm at SCL and 22 nm at Intel, a 32-bit AJIT processor from IIT Bombay at 180 nm at SCL, and VEGA processors at 130 nm at Silterra and, for the 64-bit version, 180 nm at SCL. The same release said C-DAC had made a series of ARIES development boards on the VEGA chip. On 20 March 2025 MeitY announced the DIR-V Grand Challenge, with VEGA and SHAKTI processors at its core and applications opening from 10 April.

Companies have started to build on the cores. The project’s slides list five startups spun out of the initiative, three of them in 2021: Mindgrove, Securweave and Vyoma. RISC-V International’s 2023 blog says Mindgrove uses SHAKTI cores in its chips and that InCore Semiconductors develops RISC-V processor cores. Mindgrove, founded in 2021 and incubated at IIT Madras, says it launched its Secure IoT chip in May 2024. Its product page lists a single 64-bit SHAKTI C class core at 700 MHz on a 28 nm process, with hardware encryption, secure boot and evaluation boards and stamp modules.

What the record leaves open

The label “first” belongs to IIT Madras’s 2018 announcement, which IANS reported as calling the SCL chips the first RISC-V microprocessor designed and made completely in India. Kamakoti spoke more narrowly a year later: “We have not fabricated a microprocessor from IIT,” he said, describing the chips as very small compared with one, and he named getting a processor to boot Linux as the hardest part.

The IRIS flight test that ISRO’s chairman described as planned in February 2025 has no published result in the sources opened for this article as of 5 November 2026. The three SCL chips are 180 nm designs, a process SCL describes as its baseline, and the 28 nm Mindgrove part shows the cores on a finer node, though those sources do not say where it is made.