Synopsys Says AI Cut Chip Power by Up to 25% and Cadence Claims Up to 10x Productivity, While a UC San Diego Re-test Put Google's AlphaChip First in Only Three of Nine Cases

Synopsys has said since 7 February 2023 that customers using its DSO.ai tool on 100 commercial chips saw up to 25% lower total power and more than 3x productivity. Those numbers come from Synopsys, as do most of the headline figures about artificial intelligence in chip design: Cadence’s up to 10x productivity, Google’s layouts finished in hours, NVIDIA’s adders 25% smaller. The main outside check on any of them, a UC San Diego re-run of Google’s AlphaChip, found AlphaChip had the lowest proxy cost, a composite layout score, in three of nine test cases.

A tape-out is the moment a finished chip design goes to the factory. EDA, short for electronic design automation, is the software engineers use to lay out and check circuits. Synopsys and Cadence sell it.

What Google says AlphaChip does

Google DeepMind’s post of 26 September 2024, by Anna Goldie and Azalia Mirhoseini, gave the name AlphaChip to a reinforcement-learning method, meaning one that learns by trial and reward, for placing the big circuit blocks called macros on a chip. The post says it produces layouts that are superhuman or comparable in hours instead of weeks or months of human effort. It names the last three generations of Google’s TPU AI accelerator (v5e, v5p and Trillium) and Axion, Google’s first Arm-based data-centre CPU, as chips that used it. MediaTek says it extended AlphaChip to its most advanced chips.

The method first appeared in Nature in 2021. The 2024 post came with a Nature addendum and a released pretrained checkpoint, which is a saved set of model weights. Its text gives no wirelength figures, since the TPU gains appear only in charts, and the five researchers it quotes all praise the work.

The re-test that disagreed

Chung-Kuan Cheng, Andrew Kahng and three colleagues at UC San Diego posted their first assessment on 21 February 2023 and presented it at ISPD 2023, a chip-layout symposium. Their revision of 10 March 2026 adds a stronger simulated annealing baseline, a general-purpose search method, and new benchmarks. On proxy cost, the authors report simulated annealing best in six of nine cases, AlphaChip fine-tuned from Google’s checkpoint best in two and AlphaChip trained from scratch best in one. On the largest scaled design, with 532 macros, simulated annealing gave a detailed-placement wirelength of 3,423,907 micrometres against 3,893,091 for AlphaChip. On the Ariane design at 45 nm, their Table III has simulated annealing taking 11.52 hours and AlphaChip 36.18 hours on 8 GPUs. As of November 2025, the paper says, no successful reproduction by others of the Nature claims has been published in conferences or journals.

Nature added an editor’s note on 20 September 2023 saying “the performance claims in this article have been called into question.” The next day it pulled a commentary by Kahng, who had also reviewed the Google paper and, per the retraction notice, had changed his view. Zoubin Ghahramani of Google DeepMind told Retraction Watch the company stood by the peer-reviewed results.

Google’s reply, by Goldie, Mirhoseini and Jeff Dean (15 November 2024), says the UC San Diego team did not pre-train the method, used 26 experience collectors against 512 in the Nature setup and 8 GPUs against 16, did not train to convergence and used unrepresentative test cases. It notes that invited ISPD papers are not peer-reviewed. Google also says Nature finished its investigation in April 2024 and removed the editor’s note that September, per SDxCentral’s account of Google’s timeline.

Igor Markov’s separate meta-analysis, on arXiv since June 2023, concludes that Google’s method trails human designers, simulated annealing and commercial software, and that errors in conduct and reporting undermine the Nature paper. Goldie, Mirhoseini and Dean reply that one of the papers Markov analyses was co-authored by Markov himself, which they say he does not disclose.

What Synopsys and Cadence publish

Synopsys’s February 2023 release carries three kinds of number. The aggregate claims are more than 3x productivity and up to 25% lower total power across the first 100 tape-outs, with no customer named for the 25%. SK hynix’s head of SoC, Junhyun Chun, is quoted on a 15% cell-area cut and a 5% die shrink on one project. STMicroelectronics’ Philippe d’Audigier is quoted on more than 3x faster exploration of power, performance and area trade-offs on Microsoft’s Azure cloud.

Cadence’s June 2022 release for its Cerebrus tool has MediaTek’s Harrison Hsieh reporting a 5% smaller die and more than 6% lower power on one SoC block. Renesas reported a 75% improvement in total negative slack, a timing measure, on a CPU design, and lower leakage power on a microcontroller with no percentage given. In June 2024 Cadence said Cerebrus cut leakage power by more than 10% against the best baseline flow on a Samsung SF2 design. Those are single blocks or projects chosen for release. tuput did not find an independent benchmark of DSO.ai or Cerebrus.

Agents are the 2026 pitch

Cadence launched its ChipStack agent on 10 February 2026, claiming up to 10x productivity in coding and verification, with early use at Altera, NVIDIA, Qualcomm and Tenstorrent. In the coverage tuput read, customers report verification 4x to 10x faster on selected projects, without a figure tied to a named company. By 18 August 2026, Cadence’s Paul Cunningham said about 25 substantial deployments existed, each with tens to hundreds of users. He cited a five-week assignment cut to one week, and said humans and non-agent tools still handle final sign-off.

Synopsys’s release of 28 September 2026 names AgentEngineer and Autopilot, and claims up to 50x faster verification closure and 20% higher coverage. Fujitsu’s Toshio Yoshida is quoted on a 10% to 30% productivity gain in generating RTL, the code that describes a circuit’s behaviour. Synopsys counts more than 50 engagements and plans availability by the end of 2026. These are Synopsys and partner figures, and tuput found no outside benchmark of them. How outside testers rate coding agents in general is covered in our piece on independent tests of AI agents.

NVIDIA designs with AI, and measures it itself

NVIDIA’s PrefixRL work used reinforcement learning on adders and similar circuits. Its blog of 8 July 2022 says the best 64-bit adder had 25% lower area than one from a state-of-the-art EDA tool at the same delay, and that the Hopper GPU architecture has nearly 13,000 instances of AI-designed circuits. The accompanying paper gives up to 16.0% (32-bit) and 30.2% (64-bit) lower area at the same delay. The blog says training the 64-bit case took over 32,000 GPU hours, with 256 CPUs for each GPU.

ChipNeMo, a paper by 42 NVIDIA authors first posted on 31 October 2023, adapted large language models, the kind behind chatbots, to chip design. It reports a 6.0 on a 7-point scale for an engineering-assistant chatbot and more than 70% correctness on simple EDA scripts. Its abstract says the largest model beat GPT-4 on two of three use cases. NVIDIA’s own team ran the tests.

Where Indian designers fit

The Press Information Bureau (PIB) reported on 27 January 2026 that the Design Linked Incentive scheme supports 24 startups, with startups completing 16 tape-outs that produced six chips, at nodes as advanced as 12 nm. It also counted about 2.25 crore (22.5 million) hours of use of advanced EDA tools. A PIB release of 15 July 2026 puts access to industry-standard EDA tools at 105 start-ups and MSMEs, and 315 universities training students on them, around 68,000 so far. Neither release says whether the tools include AI features, and tuput found no Indian customer figures for DSO.ai or Cerebrus. The scheme sits alongside the plants covered in our report on India’s chip fabs.

The vendors have large Indian teams. A DIGITIMES report from 22 July 2025 says Synopsys has over 6,000 engineers in Bengaluru, Hyderabad and Noida, and that its agent technologies are primarily developed by teams in those cities. Cunningham estimated about one-third of Cadence’s global workforce is in India. VerifAIX, an AI chip-verification startup founded in 2024, announced a $5 million (Rs 48 crore) seed round on 16 September 2026, co-led by Endiya Partners and Bluehill VC, and plans to grow engineering teams in the US, India and Israel. The coverage tuput read gives no performance figures for its product.

What is and is not independently measured

Two evaluations in this piece were made by people outside the companies, the UC San Diego re-test and Markov’s analysis, and Google disputes both. The rest are vendor press releases and quotes from customers who chose to be named. Synopsys plans to release AgentEngineer by the end of 2026.